Low dielectric constant film produced from silicon compounds comprising silicon-carbon bond

ABSTRACT

A method and apparatus for depositing a low dielectric constant film by reaction of an organo silane compound and an oxidizing gas. The oxidized organo silane film has excellent barrier properties for use as a liner or cap layer adjacent other dielectric layers. The oxidized organo silane film can also be used as an etch stop or an intermetal dielectric layer for fabricating dual damascene structures. The oxidized organo silane films also provide excellent adhesion between different dielectric layers. A preferred oxidized organo silane film is produced by reaction of methyl silane, CH 3 SiH 3 , and N 2 O.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is a continuation of pending U.S. Pat.application Ser. No. 10/756,122, filed Jan. 13, 2004, which is acontinuation of U.S. patent application Ser. No. 09/477,126, filed Dec.30, 1999, which is a continuation of U.S. patent application Ser. No.09/021,788, filed Feb. 11, 1998, and now issued as U.S. Pat. No.6,054,379. Furthermore, this application is related to all applicationsand patents claiming priority to Ser. No. 09/021,788.

BACKGROUND OF THE DISCLOSURE

1. Field of the Invention

The present invention relates to the fabrication of integrated circuits.More particularly, the invention relates to a process and apparatus fordepositing dielectric layers on a semiconductor substrate.

2. Background of the Invention

One of the primary steps in the fabrication of modern semiconductordevices is the formation of metal and dielectric films on asemiconductor substrate by chemical reaction of gases. Such depositionprocesses are referred to as chemical vapor deposition or CVD.Conventional thermal CVD processes supply reactive gases to thesubstrate surface where heat-induced chemical reactions take place toproduce a desired film. The high temperatures at which some thermal CVDprocesses operate can damage device structures having layers previouslyformed thereon. A preferred method of depositing metal and dielectricfilms at relatively low temperatures is plasma-enhanced CVD (PECVD)techniques such as described in U.S. Pat. No. 5,362,526. Plasma-enhancedCVD techniques promote excitation and/or disassociation of the reactantgases by the application of radio frequency (RF) energy to a reactionzone near the substrate surface, thereby creating a plasma of highlyreactive species. The high reactivity of the released species reducesthe energy required for a chemical reaction to take place, and thuslowers the required temperature for such PECVD processes.

Semiconductor device geometries have dramatically decreased in sizesince such devices were first introduced several decades ago. Sincethen, integrated circuits have generally followed the two-year,half-size rule (often called Moore's Law), which means that the numberof devices that will fit on a chip doubles every two years. Today'swafer fabrication plants are routinely producing devices having 0.35 μmand even 0.18 μm feature sizes, and tomorrow's plants soon will beproducing devices having even smaller geometries.

In order to further reduce the size of semiconductor devices onintegrated circuits, it has become necessary to use conductive materialshaving low resistivity and insulators having low k (dielectricconstant<4.0) to reduce the capacitive coupling between adjacent metallines. For example, copper is now being considered as an interconnectmaterial in place of aluminum because copper has a lower resistivity andhigher current carrying capacity. However, these materials present newproblems for integrated circuit manufacturing processes. For example,many low k dielectric materials are porous and are preferably protectedby liner layers to prevent diffusion of metals. Conventional linerlayers, such as SiN, have higher dielectric constants, and thecombination of low k dielectric layers with high k dielectric linerlayers may result in little or no improvement in the overall stackdielectric constant and capacitive coupling.

As shown in FIG. 1A, International Publication Number WO 94/01885describes a PECVD process for depositing a multi-component dielectriclayer wherein a silicon dioxide (SiO₂) liner layer 2 is first depositedon a patterned metal layer having metal lines 3 formed on a substrate 4.The liner layer 2 is deposited by reaction of silane (SiH₄) and nitrousoxide (N₂O). A self-planarizing low k dielectric layer 5 is thendeposited on the liner layer 2 by reaction of a silane compound and aperoxide compound. The liner layer 2 is an oxidized silane film that hasexcellent barrier properties when deposited in a manner which provides adielectric constant of about 4.5. The dielectric constant of theoxidized silane film can be decreased to about 4.1 by altering processconditions in a manner that decreases barrier properties of the film.

As shown in FIG. 1B, WO 94/01885 further describes an optional SiO₂ caplayer 6 that is deposited on the low k dielectric layer 5 by thereaction of silane and N₂O. The cap layer 6 is also an oxidized silanefilm that has excellent barrier properties when deposited in a mannerwhich provides a dielectric constant of about 4.5. Both the liner layer2 and the cap layer 6 have a dielectric constant greater than 4.0 andthe high dielectric constant layers substantially detract from thebenefit of the low k dielectric layer.

The benefit of some low k dielectric materials is further compromised bylow oxide content which makes the material inadequate as an etch stoplayer. Silicon nitride has been the etch stop material of choice for usewith low k dielectric materials. However, the silicon nitride disposedbetween low k dielectric layers is within the fringing field between theinterconnects. Silicon nitride has a relatively high dielectric constant(dielectric constant of about 7) compared to the surrounding dielectric,and it has been discovered that the silicon nitride may significantlyincrease the capacitive coupling between interconnect lines, even whenan otherwise low k dielectric material is used as the primary insulator.This may lead to cross talk and/or resistance-capacitance (RC) delaywhich degrades the overall performance of the device.

As devices get smaller, liner layers, cap layers, and etch stop layerscontribute more to the overall dielectric constant of μa multi-componentdielectric layer. There remains a need for low k dielectric layers whichhave excellent barrier properties for use as liner or cap layers. Therealso remains a need for low k dielectric layers which have sufficientoxide content for use as etch stop layers. Ideally, the low k dielectriclayers would be compatible with existing low k dielectric materials andcould be deposited in the same chambers as existing low k dielectricmaterials.

SUMMARY OF THE INVENTION

The present invention provides a method and apparatus for deposition ofa low dielectric constant layer which is produced by oxidation of anorgano silane compound during plasma enhanced chemical vapor deposition.The oxidized organo silane layers have excellent barrier properties foruse as a liner or cap layer adjacent other dielectric layers such asporous low k dielectric layers. In addition, the oxidized organo silanelayers have can be used as an etch stop layer, as an adhesive layerbetween different layers, or as an intermetal dielectric layer. Apreferred oxidized organ silane layer is produced by reaction of methylsilane, CH₃SiH₃, and nitrous oxide, N₂O.

In a preferred embodiment, a low k dielectric layer is deposited on apatterned metal layer by reaction of an organo silane compound and anoxidizing compound. A self-planarizing dielectric layer is thendeposited in the same chamber by reaction of an organo-silane compoundand a peroxide bonding compound. The self-planarizing dielectric layeris optionally capped in the same chamber by further reaction of theorgano silane compound and the oxidizing compound. The liner and caplayers provide strength to the self-planarizing dielectric layer duringannealing of the self-planarizing dielectric layer. After annealing, theliner and cap layers serve as diffusion barriers which protect theself-planarizing dielectric layer.

The present invention further provides an etch stop material whichprovides a reliable dual damascene structure while minimizing thecontribution of the etch stop layer to the capacitive coupling betweeninterconnect lines. In a preferred embodiment, a low k dielectric film,such as an amorphous carbon (α-C) or amorphous fluorinated carbon (α-FC)film is used as the etch stop below an intermetal dielectric (IMD).Other low k materials, such as parylene, AF₄, BCB, or PAE, or high kmaterials, such as oxynitride and silicon carbide, may also be used withthe etch stop material.

A preferred etch stop process sequence comprises forming a dualdamascene structure by depositing a first dielectric layer, such asparylene or a fluorinated silicate glass (FSG) layer, on a substrate,depositing the low k dielectric etch stop of the present invention onthe first dielectric layer, patterning the etch stop to define thecontacts/vias, depositing a second layer of a dielectric, patterning aresist layer on the second layer of dielectric to define one or moreinterconnects, and etching the interconnects and contacts/vias. Theinterconnects are etched down to the etch stop, and then the etchingcontinues past the patterned etch stop to define the contacts/vias. Oncethe dual damascene structure has been formed, a barrier layer ispreferably deposited conformably in the structure prior to filling thestructure with copper to isolate the copper from other materials, suchas silicon. The upper surface is then planarized using chemicalmechanical polishing techniques.

The invention further provides an intermetal dielectric materialcomprising the low k dielectric film which is deposited on aconventional etch stop such as silicon oxide or silicon nitride. The lowk dielectric film can also be deposited as a thin adhesive layer.

BRIEF DESCRIPTION OF THE DRAWINGS

So that the manner in which the above recited features, advantages andobjects of the present invention are attained and can be understood indetail, a more particular description of the invention, brieflysummarized above, may be had by reference to the embodiments thereofwhich are illustrated in the appended drawings.

It is to be noted, however, that the appended drawings illustrate onlytypical embodiments of this invention and are therefore not to beconsidered limiting of its scope, for the invention may admit to otherequally effective embodiments.

FIG. 1A-1B (Prior Art) are schematic diagrams of dielectric layersdeposited on a substrate by the processes known in the art;

FIG. 2 is a cross-sectional diagram of an exemplary CVD plasma reactorconfigured for use according to the present invention;

FIG. 3 is a diagram of the system monitor of the CVD plasma reactor ofFIG. 2;

FIG. 4 is a flowchart of a process control computer program product usedin conjunction with the exemplary CVD plasma reactor of FIG. 2;

FIG. 5 is a flow chart illustrating steps undertaken in depositing linerand cap layers in a gap filling process according to one embodiment ofthe present invention;

FIG. 6A-6E is a schematic diagram of the layers deposited on a substrateby the process of FIG. 5;

FIG. 7 is a cross sectional view showing a dual damascene structurecomprising the low k dielectric layers of the present invention;

FIGS. 8A-8H are cross sectional views showing one embodiment of a dualdamascene deposition sequence of the present invention;

FIG. 9 is a cross sectional view showing an adhesive layer comprisingthe low k dielectric layers of the present invention between a premetaldielectric layer and an intermetal dielectric layer; and

FIGS. 10A-10H are cross sectional views showing a dual damascenedeposition sequence wherein the low k dielectric film of the presentinvention is used to adhere an intermetal dielectric film to aconventional etch stop.

For a further understanding of the present invention, reference shouldbe made to the ensuing detailed description.

DESCRIPTION OF A PREFERRED EMBODIMENT

The present invention provides a method and apparatus for depositing alow dielectric constant layer which has excellent barrier properties andhigh oxide content. The low dielectric layer is an oxidized organosilane layer that can be used as a lining layer adjacent otherdielectric materials, as an etch stop layer adjacent dielectricmaterials having lower oxide content, as an intermetal dielectric layer,and as an adhesion layer between different materials. The oxidizedorgano silane material is deposited by oxidation of an organo silanecompound which does not fully oxidize. Carbon, including some organofunctional groups, which remains in the oxidized organo silane layercontribute to low dielectric constants and excellent barrier properties.

The organo silane compounds generally include the structure:

wherein —C— is included in an organo group and some C—Si bonds are notbroken during oxidation. Preferably —C— is included in an alkyl, such asmethyl or ethyl, or an aryl, such as phenyl. Suitable organo groups alsocan include alkenyl and cyclohexenyl groups and functional derivatives.The preferred organo silane compounds have the structureSiH_(a)(CH₃)_(b)(C₂H₅)_(c)(C₆H₅)_(d), where a=1 to 3, b=0 to 3, c=0 to3, d=0 to 3, and a+b+c+d=4, or the structureSi₂H_(e)(CH₃)_(f)(C₂H₅)_(g)(C₆H₅)_(h), where e=1 to 5, f=0 to 5, g=0 to5, h=0 to 5, and e+f+g+h=6. Preferred organo silane compounds includemethyl silane compounds having the structure SiH_(n)(CH₃)_(4-n), wheren=1 to 3, or the structure Si₂H_(m)(CH₃)_(6-m), where m=1 to 5. The mostpreferred organo silane compound is methyl silane, CH₃SiH₃. The organosilane compounds are oxidized during deposition by reaction with oxygen(O₂) or oxygen containing compounds such as nitrous oxide (N₂O),preferably N₂O, such that the carbon content of the deposited film isfrom 1 to 50% by atomic weight, preferably about 20%. The oxidizedorgano silane layer has a dielectric constant of about 3.0 and hasexcellent barrier properties. The oxidized organo silane layers furtherhave high oxide contents in comparison to conventional low k dielectriclayers and good adhesion properties.

The present invention further provides a substrate processing systemhaving a plasma reactor including a reaction zone, a substrate holderfor positioning a substrate in the reaction zone, and a vacuum system.The processing system further comprises a gas/liquid distribution systemconnecting the reaction zone of the vacuum chamber to supplies of anorgano silane compound, an oxidizing gas, and an inert gas, and an RFgenerator coupled to the gas distribution system for generating a plasmain the reaction zone. The processing system further comprises acontroller comprising a computer for controlling the plasma reactor, thegas distribution system, and the RF generator, and a memory coupled tothe controller, the memory comprising a computer usable mediumcomprising a computer readable program code for selecting the processsteps of depositing a low dielectric constant film with a plasma of anorgano silane compound and an oxidizing gas.

The processing system may further comprise in one embodiment computerreadable program code for selecting the process steps of depositing aliner of the oxidized organo silane compound, depositing a differentdielectric layer, and optionally depositing a capping layer of theoxidized organo silane compound.

Further description of the invention will be directed toward specificembodiments.

Exemplary CVD Plasma Reactor

One suitable CVD plasma reactor in which a method of the presentinvention can be carried out is shown in FIG. 2, which is a vertical,cross-section view of a parallel plate chemical vapor deposition reactor10 having a high vacuum region 15. Reactor 10 contains a gasdistribution manifold 11 for dispersing process gases through perforatedholes in the manifold to a substrate or wafer (not shown) that rests ona substrate support plate or susceptor 12 which is raised or lowered bya lift motor 14. A liquid injection system (not shown), such astypically used for liquid injection of TEOS, may also be provided forinjecting a liquid organo silane compound. The preferred methyl silanesand ethyl silanes are gases.

The reactor 10 includes heating of the process gases and substrate, suchas by resistive heating coils (not shown) or external lamps (not shown).Referring to FIG. 2, susceptor 12 is mounted on a support stem 13 sothat susceptor 12 (and the wafer supported on the upper surface ofsusceptor 12) can be controllably moved between a lowerloading/off-loading position and an upper processing position which isclosely adjacent to manifold 11.

When susceptor 12 and the wafer are in processing position 14, they aresurrounded by an insulator 17 and process gases exhaust into a manifold24. During processing, gases inlet to manifold 11 are uniformlydistributed radially across the surface of the wafer. A vacuum pump 32having a throttle valve controls the exhaust rate of gases from thechamber.

Before reaching manifold 11, deposition and carrier gases are inputthrough gas lines 18 into a mixing system 19 where they are combined andthen sent to manifold 11. Generally, the process gases supply lines 18for each of the process gases include (i) safety shut-off valves (notshown) that can be used to automatically or manually shut off the flowof process gas into the chamber, and (ii) mass flow controllers (alsonot shown) that measure the flow of gas through the gas supply lines.When toxic gases are used in the process, several safety shut-off valvesare positioned on each gas supply line in conventional configurations.

The deposition process performed in reactor 10 can be either a thermalprocess or a plasma enhanced process. In a plasma process, a controlledplasma is typically formed adjacent to the wafer by RF energy applied todistribution manifold 11 from RF power supply 25 (with susceptor 12grounded). Alternatively, RF power can be provided to the susceptor 12or the RF power can be split between different components. RF powersupply 25 can supply either single or mixed frequency RF power toenhance the decomposition of reactive species introduced into the highvacuum region 15. A mixed frequency RF power supply typically suppliespower at a high RF frequency (RF1) of 13.56 MHz and at a low RFfrequency (RF2) of 360 KHz.

Typically, any or all of the chamber lining, gas inlet manifoldfaceplate, support stem 13, and various other reactor hardware is madeout of material such as aluminum or anodized aluminum. An example ofsuch a CVD reactor is described in U.S. Pat. No. 5,000,113, entitled“Thermal CVD/PECVD Reactor and Use for Thermal Chemical Vapor Depositionof Silicon Dioxide and In-situ Multi-step Planarized Process,” issued toWang et al. And assigned to Applied Materials, Inc., the assignee of thepresent invention.

The lift motor 14 raises and lowers susceptor 12 between a processingposition and a lower, wafer-loading position. The motor, the gas mixingsystem 19, and the RF power supply 25 are controlled by a systemcontroller 34 over control lines 36. The reactor includes analogassemblies, such as mass flow controllers (MFCs) and RF generators, thatare controlled by the system controller 34 which executes system controlsoftware stored in a memory 38, which in the preferred embodiment is ahard disk drive. Motors and optical sensors are used to move anddetermine the position of movable mechanical assemblies such as thethrottle valve of the vacuum pump 32 and motor for positioning thesusceptor 12.

The system controller 34 controls all of the activities of the CVDreactor and a preferred embodiment of the controller 34 includes a harddisk drive, a floppy disk drive, and a card rack. The card rack containsa single board computer (SBC), analog and digital input/output boards,interface boards and stepper motor controller boards. The systemcontroller conforms to the Versa Modular Europeans (VME) standard whichdefines board, card cage, and connector dimensions and types. The VMEstandard also defines the bus structure having a 16-bit data but and24-bit address bus.

The system controller 34 operates under the control of a computerprogram stored on the hard disk drive 38. The computer program dictatesthe timing, mixture of gases, RF power levels, susceptor position, andother parameters of a particular process. The interface between a userand the system controller is via a CRT monitor 40 and light pen 44 whichare depicted in FIG. 3. In the preferred embodiment a second monitor 42is used, the first monitor 40 being mounted in the clean room wall forthe operators and the other monitor 42 behind the wall for the servicetechnicians. Both monitors 40, 42 simultaneously display the sameinformation but only one light pen 44 is enabled. The light pen 44detects light emitted by CRT display with a light sensor in the tip ofthe pen. To select a particular screen or function, the operator touchesa designated area of the display screen and pushes the button on the pen44. The touched area changes its highlighted color, or a new menu orscreen is displayed, confirming communication between the light pen andthe display screen.

Referring to FIG. 4, the process can be implemented using a computerprogram product 410 that runs on, for example, the system controller 34.The computer program code can be written in any conventional computerreadable programming language such as for example 68000 assemblylanguage, C, C++, or Pascal. Suitable program code is entered into asingle file, or multiple files, using a conventional text editor, andstored or embodied in a computer usable medium, such as a memory systemof the computer. If the entered code text is in a high level language,the code is compiled, and the resultant compiler code is then linkedwith an object code of precompiled windows library routines. To executethe linked compiled object code, the system user invokes the objectcode, causing the computer system to load the code in memory, from whichthe CPU reads and executes the code to perform the tasks identified inthe program.

FIG. 4 shows an illustrative block diagram of the hierarchical controlstructure of the computer program 410. A user enters a process setnumber and process chamber number into a process selector subroutine 420in response to menus or screens displayed on the CRT monitor 40 by usingthe light pen 44 interface. The process sets are predetermined sets ofprocess parameters necessary to carry out specified processes, and areidentified by predefined set numbers. The process selector subroutine420 the (i) selects a desired process chamber on a cluster tool such asan Centura™ platform (available from Applied Materials, Inc.), and (ii)selects a desired set of process parameters needed to operate theprocess chamber for performing the desired process. The processparameters for performing a specific process relate to processconditions such as, for example, process gas composition and flow rates,temperature, pressure, plasma conditions such as RF bias power levelsand magnetic field power levels, cooling gas pressure, and chamber walltemperature and are provided to the user in the form of a recipe. Theparameters specified by the recipe are entered utilizing the lightpen/CRT monitor interface.

The signals for monitoring the process are provided by the analog inputand digital input boards of system controller and the signals forcontrolling the process are output on the analog output and digitaloutput boards of the system controller 34.

A process sequencer subroutine 430 comprises program code for acceptingthe identified process chamber and set of process parameters from theprocess selector subroutine 420, and for controlling operation of thevarious process chambers. Multiple users can enter process set numbersand process chamber numbers, or a user can enter multiple processchamber numbers, so the sequencer subroutine 430 operates to schedulethe selected processes in the desired sequence. Preferably the sequencersubroutine 430 includes computer readable program code to perform thesteps of (i) monitoring the operation of the process chambers todetermine if the chambers are being used, (ii) determining whatprocesses are being carried out in the chambers being used, and (iii)executing the desired process based on availability of a process chamberand type of process to be carried out. Conventional methods ofmonitoring the process chambers can be used, such as polling. Whenscheduling which process is to be executed, the sequencer subroutine 430can be designed to take into consideration the present condition of theprocess chamber being used in comparison with the desired processconditions for a selected process, or the age of each particular userentered request, or any other relevant factor a system programmerdesires to include for determining the scheduling priorities.

Once the sequencer subroutine 430 determines which process chamber andprocess set combination is going to be executed next, the sequencersubroutine 430 causes execution of the process set by passing theparticular process set parameters to a chamber manager subroutine 440which controls multiple processing tasks in a process chamber 10according to the process set determined by the sequencer subroutine 430.For example, the chamber manager subroutine 440 comprises program codefor controlling CVD process operations in the process chamber 10. Thechamber manager subroutine 440 also controls execution of variouschamber component subroutines which control operation of the chambercomponent necessary to carry out the selected process set. Examples ofchamber component subroutines are susceptor control subroutine 450,process gas control subroutine 460, pressure control subroutine 470,heater control subroutine 480, and plasma control subroutine 490. Thosehaving ordinary skill in the art would readily recognize that otherchamber control subroutines can be included depending on what processesare desired to be performed in the reactor 10.

In operation, the chamber manager subroutine 440 selectively schedulesor calls the process component subroutines in accordance with theparticular process set being executed. The chamber manager subroutine440 schedules the process component subroutines similarly to how thesequencer subroutine 430 schedules which process chamber 10 and processset is to be executed next. Typically, the chamber manager subroutine440 includes steps of monitoring the various chamber components,determining which components needs to be operated based on the processparameters for the process set to be executed, and causing execution ofa chamber component subroutine responsive to the monitoring anddetermining steps.

Operation of particular chamber components subroutines will now bedescribed with reference to FIG. 4. The susceptor control positioningsubroutine 450 comprises program code for controlling chamber componentsthat are used to load the substrate onto the susceptor 12, andoptionally to lift the substrate to a desired height in the reactor 10to control the spacing between the substrate and the gas distributionmanifold 11. When a substrate is loaded into the reactor 10, thesusceptor 12 is lowered to receive the substrate, and thereafter, thesusceptor 12 is raised to the desired height in the chamber, to maintainthe substrate at a first distance or spacing from the gas distributionmanifold 11 during the CVD process. In operation, the susceptor controlsubroutine 450 controls movement of the susceptor 12 in response toprocess set parameters that are transferred from the chamber managersubroutine 440.

The process gas control subroutine 460 has program code for controllingprocess gas composition and flow rates. The process gas controlsubroutine 460 controls the open/close position of the safety shut-offvalves, and also ramps up/down the mass flow controllers to obtain thedesired gas flow rate. The process gas control subroutine 460 is invokedby the chamber manager subroutine 440, as are all chamber componentssubroutines, and receives from the chamber manager subroutine processparameters related to the desired gas flow rates. Typically, the processgas control subroutine 460 operates by opening the gas supply lines, andrepeatedly (i) reading the necessary mass flow controllers, (ii)comparing the readings to the desired flow rates received from thechamber manager subroutine 440, and (iii) adjusting the flow rates ofthe gas supply lines as necessary. Furthermore, the process gas controlsubroutine 460 includes steps for monitoring the gas flow rates forunsafe rates, and activating the safety shut-off valves when an unsafecondition is detected.

In some processes, an inert gas such as helium or argon is flowed intothe reactor 10 to stabilize the pressure in the chamber before reactiveprocess gases are introduced into the chamber. For these processes, theprocess gas control subroutine 460 is programmed to include steps forflowing the inert gas into the chamber 10 for an amount of timenecessary to stabilize the pressure in the chamber, and then the stepsdescribed above would be carried out. Additionally, when a process gasit to be vaporized from a liquid precursor, for example phenyl silane,the process gas control subroutine 460 would be written to include stepsfor bubbling a delivery gas such as helium through the liquid precursorin a bubbler assembly. For this type of process, the process gas controlsubroutine 460 regulates the flow of the delivery gas, the pressure inthe bubbler, and the bubbler temperature in order to obtain the desiredprocess gas flow rates. As discussed above, the desired process gas flowrates are transferred to the process gas control subroutine 460 asprocess parameters. Furthermore, the process gas control subroutine 460includes steps for obtaining the necessary delivery gas flow rate,bubbler pressure, and bubbler temperature for the desired process gasflow rate by accessing a stored table containing the necessary valuesfor a given process gas flow rate. Once the necessary values areobtained, the delivery gas flow rate, bubbler pressure and bubblertemperature are monitored, compared to the necessary values and adjustedaccordingly.

The pressure control subroutine 470 comprises program code forcontrolling the pressure in the reactor 10 by regulating the size of theopening of the throttle valve in the exhaust pump 32. The size of theopening of the throttle valve is set to control the chamber pressure tothe desired level in relation to the total process gas flow, size of theprocess chamber, and pumping set point pressure for the exhaust pump 32.When the pressure control subroutine 470 is invoked, the desired, ortarget pressure level is received as a parameter from the chambermanager subroutine 440. The pressure control subroutine 470 operates tomeasure the pressure in the reactor 10 by reading one or moreconventional pressure manometers connected to the chamber, compare themeasure value(s) to the target pressure, obtain PID (proportional,integral, and differential) values from a stored pressure tablecorresponding to the target pressure, and adjust the throttle valveaccording to the PID values obtained from the pressure table.Alternatively, the pressure control subroutine 470 can be written toopen or close the throttle valve to a particular opening size toregulate the reactor 10 to the desired pressure.

The heater control subroutine 480 comprises program code for controllingthe temperature of the heat modules or radiated heat that is used toheat the susceptor 12. The heater control subroutine 480 is also invokedby the chamber manager subroutine 440 and receives a target, or setpoint, temperature parameter. The heater control subroutine 480 measuresthe temperature by measuring voltage output of a thermocouple located ina susceptor 12, compares the measured temperature to the set pointtemperature, and increases or decreases current applied to the heatmodule to obtain the set point temperature. The temperature is obtainedfrom the measured voltage by looking up the corresponding temperature ina stored conversion table, or by calculating the temperature using afourth order polynomial. The heater control subroutine 480 graduallycontrols a ramp up/down of current applied to the heat module. Thegradual ramp up/down increases the life and reliability of the heatmodule. Additionally, a built-in-fail-safe mode can be included todetect process safety compliance, and can shut down operation of theheat module if the reactor 10 is not properly set up.

The plasma control subroutine 490 comprises program code for setting theRF bias voltage power level applied to the process electrodes in thereactor 10, and optionally, to set the level of the magnetic fieldgenerated in the reactor. Similar to the previously described chambercomponent subroutines, the plasma control subroutine 490 is invoked bythe chamber manager subroutine 440.

The above CVD system description is mainly for illustrative purposes,and other plasma CVD equipment such as electrode cyclotron resonance(ECR) plasma CVD devices, induction-coupled RF high density plasma CVDdevices, or the like may be employed. Additionally, variations of theabove described system such as variations in susceptor design, heaterdesign, location of RF power connections and others are possible. Forexample, the wafer could be supported and heated by a resistively heatedsusceptor. The pretreatment and method for forming a pretreated layer ofthe present invention is not limited to any specific apparatus or to anyspecific plasma excitation method.

Deposition of the Oxidized Organo Silane Dielectric in a Three-Layer GapFilling Process

The oxidized organo silane layer of the present invention can be used ina three-layer gap filling process as shown in FIG. 5 using the PECVDchamber of FIG. 2. Referring to FIG. 5, a wafer is positioned 200 in thereactor 10 and an oxidized organo silane layer having a low dielectricconstant is deposited 205 by a PECVD process from a plasma comprising anorgano silane compound, such as methyl silanes, ethyl silanes, or phenylsilanes, and an oxidizing gas. The deposition step 205 can include acapacitively coupled plasma or both an inductively and a capacitivelycoupled plasma in the process chamber 15 according to methods known inthe art. An inert gas such as helium is commonly used in the PECVDdeposition to assist in plasma generation. A gap fill layer is thendeposited 210 on the liner layer by known methods. The gap fill layer ispreferably self-planarizing, such as spin-on polymers or porous oxidesdeposited in liquid form by reaction of methyl silane and hydrogenperoxide. A cap layer is then deposited 215 on the gap fill layer,preferably using the same process for depositing the lining layer. Thewafer is then removed 220 from the reactor 10.

Referring to FIGS. 6A-6E, the three-layer gap filling process provides aPECVD lining layer 300 of the oxidized organo silane polymer. The lininglayer 300 acts as an isolation layer between a subsequent PECVD gap filllayer 302 and the underlying substrate surface 304 and metal lines 306,308, 310 formed on the substrate surface. The gap fill layer 302 iscapped by a PECVD capping layer 312 of the oxidized organo silanepolymer. This process is implemented and controlled using a computerprogram stored in the memory 38 of a computer controller 34 for a CVDreactor 10.

Referring to FIG. 6A, the PECVD lining layer 300 is deposited in thereactor 10 by introducing an organo silane compound such as CH₃SiH₃, anoxidizing gas such as N₂O, and a carrier gas such as helium. Thesubstrate is maintained at a temperature of from about −10 to about 450°C., and preferably is maintained at a temperature of approximately 0° C.throughout the deposition of the PECVD lining layer. The PECVD lininglayer 300 is deposited with a process gas that includes a mixture of theorgano silane compound at a flow rate of about 5 sccm to about 500 sccmand the oxidizing gas at a flow rate of about 5 sccm to about 2000 sccm.The process gases are carried by an inert gas such He, Ar, Ne, or arelatively inert gas such as nitrogen, which are typically notincorporated into the film, at a flow rate of from about 0.2 to about 20Ipm. The process gases react at a pressure from about 0.2 to about 20Torr to form a conformal polymer layer on the substrate surface 304 andmetal lines 306, 308, 310, on the substrate surface. The reaction isplasma enhanced with a power density ranging from 0.05 W/cm² to 1000W/cm², preferably about 0.3 W/cm².

For an 8″ single wafer chamber, the high frequency RF source ofapproximately 13.56 MHz is preferably driven at about 30 to about 500 Wand a low frequency RF source of about 350 KHz to MHz is preferablydriven at about 0 to about 500 W. In a currently preferred embodiment,the high frequency RF source is driven at about 50-150 W, while the lowfrequency RF source is driven at about 0-100 W.

The above process conditions result in the deposition of a PECVD lininglayer 300 (at about 2000 Å per minute) with improved barriercharacteristics for the subsequent deposition of the PECVD gap fillinglayer 302.

Referring to FIG. 6B, the PECVD gap filling layer 302 is deposited usingsimilar reactor conditions as used for depositing the liner layer 300.The process gases for the gap filling layer 302 are preferably SiH₄, orCH₃SiH₃, and 50 wt % of hydrogen peroxide (H₂O₂) which is vaporized andmixed with an inert carrier gas, such as helium. However, the gapfilling layer can be any dielectric layer which has an acceptabledielectric constant. The process gas flows range from 0-2000 sccm forHe, 10-200 sccm for CH₃SiH₃, and 0.1 to 3 g/min. for H₂O₂. The preferredgas flows range from 100-500 sccm for He, 20-100 sccm for CH₃SiH₃, and0.1 to 1 g/min. for H₂O₂. These flow rates are given for a chamberhaving a volume of approximately 5.5 to 6.5 liters. Preferably, reactor10 is maintained at a pressure of about 0.2 to about 5 torr duringdeposition of the PECVD gap filling layer 302. The gap filling layer 302may be partially cured as shown in FIG. 6C to remove solvents such aswater prior to deposition of a cap layer 312 as shown in FIG. 6D. Curingis done in the reactor 10 by pumping under an inert gas atmosphere under10 Torr.

Referring to FIG. 6D, after deposition of the PECVD gap filling layer302, the reactor 10 optionally resumes deposition of the oxidized organosilane layer of the present invention for deposition of a capping layer312. Referring to FIG. 6E, after deposition of the capping layer, ifany, the gap fill layer 302 is preferably annealed in a furnace oranother chamber at a temperature from about 100 to about 450° C. todrive off remaining solvent such as water. Of course, processingconditions will vary according to the desired characteristics of thedeposited films.

Deposition of a Dual Damascene Structure

A dual damascene structure which includes an oxidized organo silanelayers as an etch stop or as an intermetal dielectric layer is shown inFIG. 7. When the oxidized organo silane is used as an etch stop, a firstdielectric layer 510 is deposited on a substrate 512 and then theoxidized organo silane etch stop 514 is deposited on the firstdielectric layer. The etch stop is then pattern etched to define theopenings of the contacts/vias 516. A second dielectric layer 518 is thendeposited over the patterned etch stop and then pattern etched byconventional methods to define the interconnect lines 520. A single etchprocess is then performed to define the interconnects down to the etchstop and to etch the unprotected dielectric exposed by the patternedetch stop to define the contacts/vias.

Referring again to FIG. 7, the damascene structure alternativelyincludes the oxidized organo silane as an intermetal dielectric. A firstdielectric layer 510, preferably consisting of the oxidized organosilane, is deposited on a substrate 512 and then a conventional siliconoxide or silicon nitride etch stop 514 is deposited on the firstdielectric layer. The etch stop is then patterned to define the openingsof the contacts/vias 516. A second dielectric layer 518, consisting ofthe oxidized organo silane, is then deposited over the patterned etchstop and then patterned to define the interconnect lines 520. A singleetch process is then performed to define the interconnects down to theetch stop and to etch the unprotected dielectric exposed by thepatterned etch stop to define the contacts/vias.

A preferred dual damascene structure fabricated in accordance with theinvention includes a lining layer as shown in FIG. 8H, and the method ofmaking the structure is sequentially depicted schematically in FIGS.8A-8H, which are cross sectional views of a substrate having the stepsof the invention formed thereon.

As shown in FIG. 8A, an initial first dielectric layer 510, such asparylene, FSG, silicon oxide, or the like, is deposited on the substrate512 to a thickness of about 5,000 to about 10,000 Å, depending on thesize of the structure to be fabricated. As shown in FIG. 8B, the low ketch stop 514, which is the oxidized organo silane layer, is thendeposited on the first dielectric layer to a thickness of about 200 toabout 1000 Å. Low k etch stop 514 is then pattern etched to define thecontact/via openings 516 and to expose first dielectric layer 510 in theareas where the contacts/vias are to be formed as shown in FIG. 8C.Preferably, low k etch stop 514 is pattern etched using conventionalphotolithography and etch processes using fluorine, carbon, and oxygenions. After low k etch stop 514 has been etched to pattern thecontacts/vias and the photo resist has been removed, a second dielectriclayer 518 is deposited over etch stop 514 to a thickness of about 5,000to about 10,000 Å as shown in FIG. 8D. A second dielectric layer 518 isthen patterned to define interconnect lines 520, preferably usingconventional photolithography processes with a photo resist layer 522 asshown in FIG. 8E. The interconnects and contacts/vias are then etchedusing reactive ion etching or other anisotropic etching techniques todefine the metallization structure (i.e., the interconnect andcontact/via) as shown in FIG. 8F. Any photo resist or other materialused to pattern the etch stop 514 or the second dielectric layer 518 isremoved using an oxygen strip or other suitable process.

The metallization structure is then formed with a conductive materialsuch as aluminum, copper, tungsten or combinations thereof. Presently,the trend is to use copper to form the smaller features due to the lowresistivity of copper (1.7 μΩ-cm compared to 3.1 μΩ-cm for aluminum).Preferably, as shown in FIG. 8G, a barrier layer 524 of the oxidizedorgano silane material, or other suitable barrier is first depositedconformally in the metallization pattern to prevent copper migrationinto the surrounding silicon and/or dielectric material. Thereafter,copper is deposited using either chemical vapor deposition, physicalvapor deposition, electroplating, or combinations thereof to form theconductive structure. Once the structure has been filled with copper orother metal, the surface is planarized using chemical mechanicalpolishing, as shown in FIG. 8H.

Deposition of Adhesive Layers

A dual damascene structure which includes an oxidized organo silanelayer as an adhesive layer between a premetal dielectric layer and anintermetal dielectric layer is shown in FIG. 9. The oxidized organosilane adhesive layer 612 is deposited on a premetal dielectric layer610 such as a conventional PSG or BPSG layer. An intermetal dielectriclayer 614, preferably a low k dielectric polymer layer, is thendeposited over the adhesive layer 612. A conventional silicon oxide orsilicon nitride etch stop 616 and then patterned by conventional methodsto define vias 620. A second intermetal dielectric layer 622, preferablythe low k dielectric polymer, is then deposited over the patterned etchstop and then patterned to define the interconnect lines. A single etchprocess is then performed to define the interconnects down to the etchstop and to etch the unprotected dielectric exposed by the patternedetch stop to define the contacts/vias prior to metallization.

A preferred dual damascene structure comprising an adhesive layer inaccordance with the invention is shown in FIG. 10H, and the method ofmaking the structure is sequentially depicted schematically in FIGS.10A-10H, which are cross sectional views of a substrate having the stepsof the invention formed thereon.

As shown in FIG. 10A, an initial first intermetal dielectric layer 710,such as parylene, FSG, silicon oxide, or the like, is deposited on asubstrate 712 to a thickness of about 5,000 to about 10,000 Å, dependingon the size of the structure to be fabricated. As shown in FIG. 10B, alow k adhesive layer 714, which is the oxidized organo silane layer, isthen deposited on the first intermetal dielectric layer 710 to athickness of about 50 to about 200 Å. A conventional silicon oxide orsilicon nitride etch stop 716 is the deposited on the adhesive layer 714to a thickness of about 50 to about 200 Å. A second low k adhesive layer718, which is the oxidized organo silane layer, is then deposited on theetch stop 716 to a thickness of about 50 to about 200 Å. The etch stop716 and adhesive layers 714, 718 are then pattern etched to define thecontact/via openings 720 and to expose first intermetal dielectric layer710 in the areas where the contacts/vias are to be formed as shown inFIG. 10C. Preferably, the etch stop 716 is pattern etched usingconventional photolithography and etch processes using fluorine, carbon,and oxygen ions. After the etch stop 716 and adhesive layers 714, 718have been etched to pattern the contacts/vias and the photo resist hasbeen removed, a second intermetal dielectric layer 722 is deposited oversecond adhesive layer 718 to a thickness of about 5,000 to about 10,000Å as shown in FIG. 10D. The second intermetal dielectric layer 722 isthen patterned to define interconnect lines 724, preferably usingconventional photolithography processes with a photo resist layer 726 asshown in FIG. 10E. The interconnects and contacts/vias are then etchedusing reactive ion etching or other anisotropic etching techniques todefine the metallization structure (i.e., the interconnect andcontact/via) as shown in FIG. 10F. Any photo resist or other materialused to pattern the etch stop 716 or the second intermetal dielectriclayer 722 is removed using an oxygen strip or other suitable process.

The metallization structure is then formed with a conductive materialsuch as aluminum, copper, tungsten or combinations thereof. Presently,the trend is to use copper to form the smaller features due to the lowresistivity of copper (1.7 μΩ-cm compared to 3.1 μΩ-cm for aluminum).Preferably, as shown in FIG. 10G, a barrier layer 728 of the oxidizedorgano silane material, or other suitable barrier is first depositedconformally in the metallization pattern to prevent copper migrationinto the surrounding silicon and/or dielectric material. Thereafter,copper is deposited using either chemical vapor deposition, physicalvapor deposition, electroplating, or combinations thereof to form theconductive structure. Once the structure has been filled with copper orother metal, the surface is planarized using chemical mechanicalpolishing, as shown in FIG. 10H.

The invention is further described by the following example of adeposited methyl silane film.

EXAMPLE

The following example demonstrates deposition of an oxidized organosilane film having excellent barrier and adhesion properties. Thisexample was undertaken using a chemical vapor deposition chamber, and inparticular, a CENTURA DxZTM system which includes a solid-state RFmatching unit with a two-piece quartz process kit, both fabricated andsold by Applied Materials, Inc., Santa Clara, Calif.

An oxidized methyl silane film was deposited at a chamber pressure of3.0 Torr and temperature of 0° C. from reactive gases which were flowninto the reactor as follows: Methyl silane, CH₃SiH₃, at  55 sccm Nitrousoxide, N₂O, at  300 sccm Helium, He, at  4000 sccm.

The substrate was positioned 600 mil from the gas distributionshowerhead and 80 W of high frequency power (13 MHz) was applied to theshowerhead for plasma enhanced deposition of an oxidized methyl silanelayer.

The oxidized methyl silane material was deposited at a rate of 1800 Å.The deposited film had a dielectric constant of 3.0 and a refractiveindex of 1.44. The film had a measured tensile stress of 0.8×109dynes/cm².

While the foregoing is directed to a preferred embodiment of the presentinvention, other and further embodiments of the invention may be devisedwithout departing from the basic scope thereof, and the scope thereof isdetermined by the claims which follow.

1. An integrated circuit structure, comprising: regions of dielectricmaterial separating regions of conductive material within a layer,wherein the regions of dielectric material comprise: a first dielectricmaterial comprising a porous low k dielectric material; and a seconddielectric material comprising silicon, oxygen, and carbon, wherein thesecond dielectric material forms a low k lining layer between the firstdielectric material and the regions of conductive material.
 2. Theintegrated circuit structure of claim 1, wherein the first dielectricmaterial is a spin-on porous silicon oxide.
 3. The integrated circuitstructure of claim 1, further comprising a cap layer on the firstdielectric material, the cap layer comprising the second dielectricmaterial.
 4. An integrated circuit structure, comprising: regions ofdielectric material separating regions of conductive material, whereinthe regions of dielectric material comprise: a first dielectric materialcomprising a porous low k dielectric material; a second dielectricmaterial comprising silicon, oxygen, and carbon, wherein the seconddielectric material forms a cap layer on the first dielectric material.5. The integrated circuit structure of claim 4, wherein the firstdielectric material is a spin-on porous silicon oxide.
 6. The integratedcircuit structure of claim 4, further comprising a lining layer betweenthe first dielectric material and the regions of conductive material,wherein the lining layer comprises the second dielectric material.